Flip-flops are indispensable in digital logic design. The flip-flop itself can also be regarded as a one-bit memory circuit. There are several kinds of flip-flops. In particular, a D flip-flop accepts an input and generates an output with the same value of the accepted input when it is triggered by a clock signal. Power consumption has been one of the greatest concerns for all designers when designing a flip-flop, since it is widely in use and contributes a significant portion of the total power consumption in digital circuits. In practice, the performance of a D flip-flop is commonly measured in terms of power delay product, which is the product of the average power consumption and the propagation delay measured from the triggering point of the clock signal to the occurrence of the output signal corresponding to the input signal right before the triggering edge of the clock.
FIG. 1 shows a conventional master-slave D flip-flop 100. Each of the master stage 110 and slave stage 120 has a pass gate and a memory element. The pass gate is a transmission gate driven by a clock signal. In a conventional D flip-flop, the external clock signal typically does not drive the transmission gate directly, because that will increase the capacitance of the external clock line, which is undesirable in large circuits, as large clock line capacitance will cause clock skew problem. Instead, the external clock CLK is buffered by inverting the external clock signal CLK twice with inverters Inv1.1 and Inv1.2. The memory element in each stage is formed by a feedback loop of two inverters (Inv 1.3 and Inv1.4 in the master stage, and Inv1.5 and Inv1.6 in the slave stage) and is controlled by another pass gate (pass gate 1.2 in the master stage, and pass gate 1.4 in the slave stage). When the pass gate is turned on, the feedback path is completed and the two inverters form a latch, which can serve as memory. When the clock signal CLK is low, the pass gate 1.2 will break the loop of the master memory, while the input signal D will pass through pass gate 1.1 and complete the memory write action onto the master memory at the same time. The signal written into the master memory equals to the signal D right at the moment of the rising edge of the CLK signal. When the CLK signal is high, the two stages are connected together by the pass gate 1.3. At the same time, the pass gate 1.4 will break the loop of the slave memory. As a result, the signal that has been written into the master memory will pass through the pass gate 1.3 and complete the memory-write action onto the slave memory. When the CLK signal is low again, the slave stage is isolated from the master stage and the signal is passed to the slave stage and is stored in its latch formed by Inv1.5 and Inv1.6. Such D flip-flop is known as rising edge triggered master slave D flip-flop. D flip-flop with other triggering type can be constructed similarly in the hands of the skilled engineers.
The reduction of the power consumption of the conventional master slave D flip-flop has been extensively investigated in the literature. An effective way to reduce the power consumption is to use dynamic circuit to construct the master flip-flop and simplify the static circuit of the slave flip-flop 200 as shown in FIG. 2. The master stage 210 in FIG. 2 replaces the pass gate 1.1 in FIG. 1 by a switching transistor M2.1, which is controlled by a complemented CLK signal. The feedback inverter Inv1.4 of the memory element is eliminated. In this case, the storage function is performed by the dynamic memory element constructed by the parasitic capacitor of the output of Inv2.3. The pass gate 1.2 is replaced by transistor M2.2, which is used to turn on and off the inverter Inv2.3 to complete the memory write action. Comparing to the conventional master stage as shown in FIG. 1, the one in FIG. 2 has fewer device count and smaller clock load, thus consumes less power. The slave stage 250 is similar to the conventional one, but the two transmission gates pass gate 1.3 and pass gate 1.4 in FIG. 1 are reduced from two transistors to one with switching transistor M2.3 so that the device count is further reduced and the two phase clock is not required as contrast to that in FIG. 1. However, using switching transistor may reduce output voltage across the transistor. In the other words, it would require additional power to pull the output voltage back to VDD, where VDD is the supply voltage of the D flip-flop, which is the logic 1 voltage representation in digital logic. Otherwise the circuit will be operated with reduced noise margin. To remedy the problem, inverter Inv2.3 is added to the master stage. When D is at logic 1, node x1 has a voltage of VDD-VT, where VT is the threshold voltage of the transistor M2.1. To compensate for the reduced voltage at node x1, the transistor sizes of inverter Inv2.3 is adjusted such that its noise margin is wide enough to accommodate the voltage drop at node x1. In this case, the switching transistor M2.3 of the slave stage does not suffer from the voltage drop problem and can maintain a strong driving capability to push a large output latch. At the latch of the slave stage, a weak feedback inverter Inv2.5 is used so that switching transistor M2.3 can write a different signal into the latch by using a small power.